1. Field of the Invention
The present invention belongs to the technical field of a semiconductor device, and particularly relates to a semiconductor storage device having a memory cell area containing a capacitor and a transistor, and a method of manufacturing the semiconductor storage device.
2. Description of the Related Art
In order to implement high storage capacity, a so-called stack structure in which the electrode of a capacitor constituting a memory cell is three-dimensionally formed and it is disposed while superposed on a transistor has been applied to DRAM as a representative of semiconductor storage devices.
FIG. 9 is a schematic cross-sectional view showing the conventional DRAM thus constructed.
In FIG. 9, reference symbol A represents a memory cell area and reference symbol B represents a peripheral circuit area. Reference numeral 10 represents a semiconductor substrate, reference numeral 12 represents an element separation oxide film, reference numeral 14 represents a MOS transistor for a memory cell constituting the memory cell area A, and reference numeral 16 represents a MOS transistor constituting the peripheral circuit area B. Further, reference numeral 14a represents the source/drain of the MOS transistor 14, and reference numeral 14b represents the gate of the MOS transistor 14. Reference numeral 16a represents the source/drain of the MOS transistor 16, and reference numeral 16b represents the gate of the MOS transistor 16. Reference numeral 18 represents an insulating layer, and reference numeral 20 represents a connection opening formed in the insulating layer 18 and a conductive member 22 is filled in the connection opening 20.
A cylindrical capacitance stack electrode 24 is formed at the position corresponding to the conductive member 22 on the insulating layer 18, a capacitance insulating film 26 is formed on the side surface and top surface of the capacitance stack electrode 24, and a capacitance plate electrode 28 is formed on the capacitance insulting film 26. These members construct a capacitor 30.
An insulating film (interlayer insulating film) 32 is formed on the insulating layer 18 so as to cover the capacitor 30. Since desired wires are formed on the insulating film 32, the upper surface of the insulating film 32 is flattened to prevent the wires from being broken during the wire forming process.
The process of manufacturing DRAM as described above will be described with reference to FIGS. 10 to 15.
First, as shown in FIG. 10, the element separation oxide film 12 is formed on the semiconductor substrate 10, and the MOS transistors 14, 16 and the insulating layer 18 is formed.
Subsequently, as shown in FIG. 11, the connection opening 20 is formed in the insulting layer 18, and the conductive member 22 is filled into the connection opening 20.
Subsequently, as shown in FIG. 12, the capacitance stack electrode 24 is formed at the position corresponding to the conductive member 22, the capacitance insulating film 26 is formed on the capacitance stack electrode 24, and a capacitance plate electrode 28 is formed on the capacitance insulating film 26, thereby forming the capacitor 30.
Subsequently, the interlayer insulating film 32 is formed on the insulating layer 18 as shown in FIG. 13. At this time, the upper surface of the interlayer insulating film 32 in the memory cell area A is higher than the upper surface of the interlayer insulating film 32 in the peripheral circuit area B by the amount corresponding to the height of the capacitor 30. Therefore, the interlayer insulating film 32 of the memory cell area A is subjected to an etching treatment so that the upper surface of the interlayer insulting film 32 in the memory cell area A is located at substantially the same height as the upper surface of the interlayer insulating film 32 in the peripheral circuit area B. In order to perform the etching treatment, a photoresist mask 34 is formed on the interlayer insulating film 32 in the peripheral circuit area B.
Subsequently, as shown in FIG. 14, the etching treatment is conducted on the interlayer insulating film 32 of the memory cell area A to substantially equalize the height of the interlayer insulating film 32 in the memory cell area A with the height of the interlayer insulating film 32 of the peripheral circuit area B.
Subsequently, as shown in FIG. 15, the photoresist mask 34 is removed, and if necessary, an insulating film is further deposited to thereby form the interlayer insulating film 32 having the flat upper face (surface), thereby forming DRAM as shown in FIG. 9.
The above DRAM is described in NIKKEI MICRODEVICES, November (1993), p.31.
As described above, in the conventional DRAM, the capacitance stack electrode of the capacitor constituting the memory cell is formed of a pillar-shaped conductor, and thus there occurs a large difference in height (step) between the memory cell area and the peripheral circuit area when the interlayer insulating film is formed. As a result, since it is necessary to secure the flatness of the surface of the interlayer insulating film (particularly between the memory cell area and the peripheral circuit area) in order to smoothly form wires on the interlayer insulating film in the subsequent step, a photolithography step is further needed to selectively remove the interlayer insulating film only in the memory cell area after the interlayer insulating film is deposited as described above, and thus the number of steps is increased.
Therefore, the present invention has been implemented to solve the foregoing problems of the prior art, and has an object to provide a semiconductor device in.which an insulating film such as an interlayer insulating film having a flat surface can be formed without any specific step of flattening the insulating film after the insulating film is deposited, that is, without increasing the number of steps, and a method of manufacturing the semiconductor device.
In order to attain the above object, according to a first aspect of the present invention, a semiconductor storage device having plural memory cells each containing a capacitor and a transistor is characterized in that a first insulating layer is formed so as to cover the transistor, the capacitor is formed on the first insulating layer, the capacitor contains a pillar-shaped insulating member formed on the first insulating layer, a first capacitance electrode formed on the side surface of the pillar-shaped insulating member, a capacitance insulating film formed on the first capacitance electrode and a second capacitance electrode formed on the capacitance insulating film, the first insulating layer has a connection opening formed therein, and the connection opening is filled with a conductive member for connecting the first capacitance electrode and the transistor to each other.
In the semiconductor storage device described above, a second insulating layer formed of the same insulating material as the pillar-shaped insulating member of the capacitor is preferably formed at the same height as the pillar-shaped insulating member of the capacitor on the first insulating layer in at least a part of an area other than the memory cell area containing the plural memory cells.
In the semiconductor storage device described above, the transistor is preferably a MOS transistor, and the source or drain of the MOS transistor is connected to the conductive member.
According to a second aspect of the present invention, a method of manufacturing a semiconductor storage device having plural memory cells each containing a capacitor and a transistor is characterized by comprising the steps of: forming the transistor on a semiconductor substrate; forming a first insulating layer so that the transistor is covered by the first insulating layer; forming connection openings in the first insulating layer at the positions corresponding to the respective memory cells; filling a conductive member in each of the connection openings; forming an insulating material layer on the first insulating layer; subjecting the insulating material layer to a patterning treatment to form a pillar-shaped insulating member so that a part of the surface of the conductive member filled in each of the connection openings is covered by the pillar-shaped insulating member; forming a first capacitance electrode on the side surface of the pillar-shaped insulating member, connecting the first capacitance electrode and the conductive member to each other, forming a capacitance insulating film on the first capacitance electrode, and forming a second capacitance electrode on the capacitance insulating film.
In the semiconductor storage device manufacturing method described above, the patterning treatment of the insulating material layer is preferably performed by using anisotropic etching.
In the above semiconductor storage device manufacturing method, the formation of the first capacitance electrode is preferably performed by forming a conductive material layer and patterning the conductive material layer with anisotropic etching.
In the above semiconductor storage device manufacturing method, the transistor is preferably a MOS transistor, and each connection opening is formed at the position corresponding to the source or drain of the MOS transistor.
In the above semiconductor storage device manufacturing method, it is preferable that the insulating material layer is also formed in an area other than the memory cell area containing the plural memory cells on the semiconductor substrate, and the insulating material layer is subjected to a patterning treatment so that a second insulating layer having the same height as the pillar-shaped insulating member of the capacitor remains in the area other than the memory cell area.
According to the present invention, the capacitor of the memory cell area is constructed while containing the pillar-shaped insulating member, and the pillar-shaped insulating member is formed simultaneously with formation of the interlayer insulating film in the area other than the memory cell area. Therefore, the surface flattening between the memory cell area and the other area can be easily performed without increasing the number of steps.